The present technology relates to a transistor and transistor manufacturing method. In particular, the technology relates to a transistor and transistor manufacturing method capable of reducing occurrence of the inverse narrow channel effect and kink characteristics due to scale-down.
Conventionally, with the progress of scale-down of LSIs (Large-Scale Integrated circuits), there have been demands also for scale-down of the device formation region, which is a region where MOS (Metal Oxide Semiconductor) transistors and the like are fabricated, as well as scale-down of the device isolation films which define the device formation region, on a semiconductor substrate. As a technique for implementing such scale-down of device formation regions and device isolation films, STI (Shallow Trench Isolation) process wherein a trench is formed on the semiconductor substrate and thereafter a dielectric film is buried in this trench to form the device isolation film is often used.
However, the device formation region defined by the device isolation films formed by the STI process has problems of parasitic transistors or the like. More specifically, when a device isolation film 406 is formed on a silicon substrate 401 by STI process as shown in a sectional view of FIG. 4, a side face of the silicon substrate 401 adjoins a gate electrode 408 via a gate insulator 407 at an end portion (a portion surrounded by a broken-line circle) of the device formation region adjacent to the device isolation film 406. As a result of this, an electric field derived from the gate electrode 408 is applied to the end portion of the device formation region not only from the surface but also the side face as indicated by arrow F, resulting in a concentration of the electric field. Accordingly, a so-called parasitic transistor that causes the threshold voltage to locally lower is formed at the end portion of the device formation region. As a consequence, the transistor formed in the device formation region is subject to occurrence of the inverse narrow channel effect that the threshold voltage of the transistor increasingly lowers with narrowing gate width of the transistor, or the kink characteristics that the drain current increases discontinuously in the subthreshold region of gate voltage—drain current characteristics of the transistor. This gives rise to a problem that the OFF-state current of the transistor increases, leading to an increase in LSI power consumption.
In order to solve these problems, conventionally, there has been proposed a technique for relaxing the concentration of an electric field in the end portion of the device formation region by forming the cross-sectional configuration of the end portion of the device formation region to a rounded configuration (see International Electron Device Meeting, IEDM 98, pp. 133-136).
One example of such a transistor manufacturing method for forming the cross-sectional configuration of an end portion of the device formation region into a rounded one as described above (hereinafter, referred to as first prior art) is shown in process diagrams of FIGS. 5A to 5F.
First, pad oxide 502 is formed on a silicon substrate 501 by thermal oxidation, and silicon nitride 503 is deposited thereon. After that, as shown in FIG. 5A, portions of the silicon nitride 503, the pad oxide 502 and the silicon substrate 501 positioned where a device isolation film is to be formed are etched by RIE (Reactive Ion Etching) process to form a trench 504. Subsequently, as shown in FIG. 5B, the pad oxide 502 exposed to the inner side face of the trench 504 is etched by wet etching so that the surface of the pad oxide 502 exposed to the trench 504 is moved back along the planar direction of the substrate. Then, as shown in FIG. 5C, the surface of the silicon substrate 501 exposed to the trench 504 is oxidized at temperatures of 1000 to 1100° C. in, for example, a hydrochloric-acid or other halogen-based gas atmosphere, by which thermal oxide 505 is formed. By this oxidation process, damage of the exposed surface of the silicon substrate 501 that has occurred in the etching by the RIE process can be removed and moreover corner portions of the silicon substrate 501 in end portions of the device formation region can be rounded. Subsequently, as shown in FIG. 5D, silicon oxide 506 is deposited by CVD (Chemical Vapor Deposition) process so that the trench 504 is buried. After that, the surface of the silicon oxide 506 is polished by CMP (Chemical Mechanical Polish) process, thereby making the surface of the silicon oxide 506 and the surface of the silicon nitride 503 flush with each other as shown in FIG. 5E. Then, the silicon nitride 503 is removed as shown in FIG. 5F, by which a device formation region, which is a portion where the pad oxide 502 on the silicon substrate 501 is provided, and a device isolation film formed of the silicon oxide 506, which defines the device formation region, can be obtained. By forming a source and a drain in the device formation region, a MOS transistor can be obtained.
Also, for the prevention of occurrence of the inverse narrow channel effect or kink characteristics of the transistor formed in the device formation region, there has conventionally been proposed a technique for burying portions between the side face at end portions of the device formation region and the device isolation film with oxide (see JP 2000-22153 A).
One example of such a transistor manufacturing method including the step of burying portions between the side face at end portions of the device formation region and the device isolation film with oxide is shown in FIGS. 6A to 6I (hereinafter, referred to as second prior art).
First, as shown in FIG. 6A, pad oxide 602 is formed on a silicon substrate 601 by thermal oxidation, and silicon nitride 603 is deposited on the pad oxide 602. After that, portions of the pad oxide 602, the silicon nitride 603 and the silicon substrate 601 positioned where a device isolation film is to be formed are etched by RIE process to form a trench 604. This trench 604 is formed shallow, and the portion of the silicon substrate 601 corresponding to the trench 604 is formed into such a tapered shape as to be narrowed in width increasingly toward the bottom face. Subsequently, the exposed surface of the silicon substrate 601 in the trench 604 is oxidized to form oxide 612, and thereafter, as shown in FIG. 6B, polysilicon 613 is deposited on the surface of the silicon nitride 603 and the surface of the trench 604. Then, all of the polysilicon 613 is oxidized, by which such thermal oxide 614 as shown in FIG. 6C is formed. Subsequently, the thermal oxide 614 and the oxide 612 are subjected to anisotropic etching. As a result of this, as shown in FIG. 6D, a side wall 615 made of part of the thermal oxide 614 is formed between a face of the silicon nitride 603 directed toward inside of the trench 604 and the tapered portion of the oxide 602. Then, as shown in FIG. 6E, the silicon substrate 601 exposed to the bottom of the trench 604 is further etched by RIE process so that the depth of the trench 604 is increased. The exposed surface of the silicon substrate 601 within the trench 604 of the increased depth is thermally oxidized, by which thermal oxide 605 is formed. Subsequently, as shown in FIG. 6F, silicon oxide 606 is deposited by CVD process so as to bury the trench 604 and moreover cover the surface of the silicon nitride 603. Then, as shown in FIG. 6G, the surface of the silicon oxide 606 is planarized, making the surface of the silicon nitride 603 exposed, so that the surface of the silicon oxide 606 within the trench 604 and the surface of the silicon nitride 603 are made flush with each other. Subsequently, as shown in FIG. 6H, the silicon nitride 603 is removed. As a result of this, a device isolation film made of the silicon oxide 606 is formed. Thereafter, the pad oxide 602 is removed, a well 610 is formed in the silicon substrate 601 as shown in FIG. 6I, gate oxide 607 is formed on the surface of the silicon substrate 601, and further a gate electrode 608 is formed on the gate oxide 607 and the silicon oxide 606 (device isolation film). By forming a source and a drain in the well 610, a MOS transistor can be obtained.
According to the second prior art, since the side walls 615 are formed in adjacency to end portions of the device formation region, side faces of the well 610 can be prevented from adjoining the gate electrode 608 via the thermal oxide 605 at the end portions of the device formation region. Therefore, the transistor of the device formation region is prevented from occurring the inverse narrow channel effect and kink characteristics.
However, in the first prior art, since the thermal oxide 505 for rounding the corners at the end portions of the device formation region is formed relatively thick, there is a problem that the silicon substrate 501 is consumed so that the width of the silicon substrate 501 to be used for the device formation region becomes narrow. Also, since the volume of the thermal oxide 505 formed in the trench 504 becomes about twice as much as that of consumed silicon, there is a problem that the width of the trench 504 becomes narrow. For rounding of the end portions of the device formation region, it is necessary to form the thermal oxide 505 to a specified thickness regardless of the level of the scale-down. Therefore, as the device formation region and the device isolation film decrease in width with the progress of scale-down of LSIs, decrease in width of the device formation region as well as decrease in width of the trench 504 due to the formation of the thermal oxide 505 become relatively larger, making it difficult to form devices in the device formation region, and the silicon oxide 506 becomes harder to bury into the trench 504, as further problems. Thus, with the progress of LSI scale-down, the first prior art becomes harder to apply.
Also, in the second prior art, since a deposition step for the polysilicon 613 and a thermal oxidation step for the polysilicon 613 are involved in the formation of the side walls 615, there is a problem of increased steps involved. A further problem is that the device formation region is decreased in width because of the formation of the side walls 615. Still another problem is that ensuring the width of the device formation region would cause the trench 604 to be narrower in width because of the formation of the side walls 615. Narrowed width of the trench 604 would lead to a problem that the trench 604 is further decreased in width due to a micro loading effect during the etching for increasing the depth of the trench 604. There is yet another problem that impurities would remain in the trench 604 through the deposition step and thermal oxidation step for the polysilicon 613 and the anisotropic etching step or the like, so that voids would occur in the silicon oxide 606 that has been buried within the trench 604 by CVD process. Consequently, since an attempt to implement the scale-down of the device formation region and the device isolation film along with the scale-down of LSIs would encounter difficulty in forming the device isolation film and since voids are liable to occur in the device isolation film, there is a problem that the second prior art has difficulty in implementing the scale-down of LSIs.